Title :
Comprehensive SRAM design methodology for RTN reliability
Author :
Takeuchi, Kiyoshi ; Nagumo, Toshiharu ; Hase, Takashi
Author_Institution :
Renesas Electron. Corp., Sagamihara, Japan
Abstract :
In this paper, a comprehensive design flow for achieving reliable SRAMs against random telegraph noise (RTN) is presented. The tailing information of RTN amplitude distributions is important for guardbanding, and can be directly extracted from SRAM test results. Monte Carlo simulation is in excellent agreement with the measurements, and can be used for detailed design. A simple extrapolation method for intuitive understanding of long term RTN impact is also proposed.
Keywords :
Monte Carlo methods; SRAM chips; extrapolation; integrated circuit design; integrated circuit noise; integrated circuit reliability; random noise; Monte Carlo simulation; RTN amplitude distributions; RTN reliability; comprehensive SRAM design methodology; extrapolation method; random telegraph noise; Extrapolation; Life estimation; Noise; Random access memory; Reliability; Transistors; Very large scale integration;
Conference_Titel :
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-9949-6
