An efficient manufacturing technique based on process compact model to reduce characteristic variation beyond process limit for 40 nm node mass production

Practical manufacturing technique to reduce characteristic variation of 40 nm CMOS device has been developed. Novel feed-forward (FF) system at gate formation for tight gate length control, and FF techniques at both halo implantation and Spike RTA for device centering have been applied. In addition, adjusting wafer notch angle at each critical process step has been utilized to suppress within-wafer variation. As a result, total Vth variation has been reduced by 46%.