Design of embedded memory and logic based on pattern constructs

Author

Morris, Daniel ; Vaidyanathan, Kaushik ; Lafferty, Neal ; Lai, Kafai ; Liebmann, Lars ; Pileggi, Larry

Author_Institution

Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

2011

fDate

14-16 June 2011

Firstpage

104

Lastpage

105

Abstract

Design rules become ineffective for interfacing layout design and manufacturing when complex lithography sources are used for sub-20 nm patterning. Experiments demonstrate feasibility of a construct-based design that facilitates control of process capabilities and captures layout dependent variations. Results for early 14 nm patterning experiments are shown for logic and memory circuits.

Keywords

integrated circuit layout; integrated memory circuits; lithography; logic circuits; logic design; construct-based design; embedded logic circuits; embedded memory circuits; layout design; lithography sources; pattern constructs; patterning experiments; size 14 nm; size 20 nm; Fabrics; Gratings; Layout; Lithography; Optimization; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984661

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549718