Design challenges of low-power and high-speed memory interface in advanced CMOS technology

Design requirements for low-power and high-speed memory interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low Vdd/Vth ratio, interconnect parasitics, and model accuracy of key process parameters. It is shown that careful system architecture along with appropriate circuit techniques allow mobile memory interface to meet aggressive performance and power targets with conventional technology.