High performance graphene FETs with self-aligned buried gates fabricated on scalable patterned ni-catalyzed graphene

Author

Wang, Yanjie ; Huang, Bo-Chao ; Zhang, Ming ; Miao, Congqin ; Xie, Ya-Hong ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., UCLA, Los Angeles, CA, USA

fYear

2011

fDate

14-16 June 2011

Firstpage

116

Lastpage

117

Abstract

For the first time, we report a scalable technique to fabricate graphene transistors with self-aligned buried gates process. The high performance buried-gate graphene transistor has excellent field-effect mobility of 6,100cm²/V·s and 24,000 cm²/V·s before and after subtraction of contact resistance. To the best of our knowledge, this is the highest room temperature mobility for CVD graphene FETs reported to date. This result paves the way for manufacturable high quality graphene transistor technology.

Keywords

chemical vapour deposition; contact resistance; field effect transistors; graphene; nickel; CVD graphene FET; Ni; contact resistance; field-effect mobility; graphene transistors; high-performance graphene FET; high-quality graphene transistor technology; room temperature mobility; scalable patterned nickel-catalyzed graphene; self-aligned buried gate process; Contact resistance; Etching; FETs; Logic gates; Nickel; buried gate; graphene; self-aligned; transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984667