DocumentCode
549728
Title
TSV process optimization for reduced device impact on 28nm CMOS
Author
Yu, C.L. ; Chang, C.H. ; Wang, H.Y. ; Chang, J.H. ; Huang, L.H. ; Kuo, C.W. ; Tai, S.P. ; Hou, S.Y. ; Lin, W.L. ; Liao, E.B. ; Yang, K.F. ; Wu, T.J. ; Chiou, W.C. ; Tung, C.H. ; Jeng, S.P. ; Yu, C.H.
Author_Institution
R&D, Integrated Interconnect & Packaging Div., tsmc, Hsinchu, Taiwan
fYear
2011
fDate
14-16 June 2011
Firstpage
138
Lastpage
139
Abstract
A through-silicon-via (TSV) process is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. TSV leakage, yield, C-V flat-band shift, Cu contamination, and reliability are significantly improved via process optimization. The preferred TSV processing could relax TSV stress and minimize keep-out zone (KOZ). In this study, we also address the impact of multiple-TSVs additive stress impact, TSV signal coupling effect, and TSV depletion impact to assess the power-TSV plug cell in design practice.
Keywords
CMOS integrated circuits; copper; optimisation; three-dimensional integrated circuits; CMOS; TSV process optimization; keep-out zone; reduced device impact; size 28 nm; through-silicon-via process; Additives; Copper; Couplings; MOSFET circuits; Silicon; Stress; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4244-9949-6
Type
conf
Filename
5984673
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