Author :
Yang, K.F. ; Wu, T.J. ; Chiou, W.C. ; Chen, M.F. ; Lin, Y.C. ; Tsai, F.W. ; Hsieh, C.C. ; Chang, C.H. ; Wu, W.J. ; Chen, Y.H. ; Chen, T.Y. ; Wang, H.R. ; Lin, I.C. ; Jan, S.B. ; Wang, R.D. ; Lu, Y.J. ; Shih, Y.C. ; Teng, H.A. ; Tsai, C.S. ; Chang, M.N. ;
Author_Institution :
R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
A stacked three-dimension integrated circuit (3D-IC) of 28 nm chips was demonstrated. Key enabling technologies such as through silicon via (TSV) formation, wafer thinning, redistribution layer (RDL), micro bump and joint were developed for chip stacking and interconnect functions evaluation. The excellent performances of 3D-IC yield and reliability characteristics are key milestones in promising manufacturability of 3D-IC by silicon foundry technology.
Keywords :
integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; three-dimensional integrated circuits; 3DIC technology; micro bump; redistribution layer; silicon foundry technology; size 28 nm; three-dimension integrated circuit; through silicon via formation; wafer thinning; Copper; Joints; Reliability; Silicon; Stress; Surface topography; Through-silicon vias;
