DocumentCode :
549730
Title :
Novel GAA raised source / drain sub-10-nm poly-Si NW channel TFTs with self-aligned corked gate structure for 3-D IC applications
Author :
Lu, Yi-Hsien ; Kuo, Po-Yi ; Wu, Yi-Hong ; Chen, Yi-Hsuan ; Chao, Tien-Sheng
Author_Institution :
Dept. of Electrophys., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2011
fDate :
14-16 June 2011
Firstpage :
142
Lastpage :
143
Abstract :
A novel gate-all-around raised source / drain sub-10-nm poly-Si nanowire (NW) channel TFTs with self-aligned corked gate structure (GAA RSDNW-TFTs) have been successfully demonstrated. It is through the use of a novel fabrication process requiring no advanced lithographic tools. The corked gate (CG) structure, only the poly gate pattern was etched, reduces complex of process significantly. For the first time, several properties of this 3D architecture are explored: (i) the Si NW dimension is about 7 nm × 12 nm and a superior smooth elliptical shape is obtained in the category of poly-Si NW TFTs. (ii) the temperature dependence and the instability under PBTI stress of the main electrical parameters are proposed.
Keywords :
lithography; nanowires; silicon; three-dimensional integrated circuits; travelling wave tubes; 3D IC applications; GAA raised source-drain; PBTI stress instability; Si; advanced lithographic tools; gate-all-around; nanowire channel TFT; self-aligned corked gate structure; size 10 nm; temperature dependence; Logic gates; Plasmas; Shape; Silicon; Stress; Temperature dependence; Thin film transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location :
Honolulu, HI
ISSN :
0743-1562
Print_ISBN :
978-1-4244-9949-6
Type :
conf
Filename :
5984675
Link To Document :
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