Title :
Ultra-thin buried nitride integration for multi-VT, low-variability and power management in planar FDSOI CMOSFETs
Author :
Nguyen, P. ; Andrieu, F. ; Garros, X. ; Widiez, J. ; Molas, G. ; Tisseur, R. ; Weber, O. ; Toffoli, A. ; Allain, F. ; Lafond, D. ; Dansas, H. ; Tabone, C. ; Brévard, L. ; Dechamp, J. ; Guiot, E. ; Faynot, O.
Author_Institution :
CEA-LETI, Grenoble, France
Abstract :
We highlight an original solution to adjust the threshold voltage (VT) of Fully Depleted Silicon-On-Insulator CMOS down to L=20nm gate length thanks to charge storage in a thin buried nitride layer. In particular, high performance pMOS with Ioff=500nA/μm (VT=-0.2V) are demonstrated in a gate first approach. This technique is combined with back-bias for power management and with a smart process compensation technique to improve the device variability down to σVT=4mV for L=30nm and W=500nm.
Keywords :
CMOS integrated circuits; MOSFET; silicon-on-insulator; charge storage; device variability; fully-depleted silicon-on-insulator CMOS; high-performance pMOS; planar FDSOI CMOSFET; power management; size 20 nm; size 30 nm; size 500 nm; smart process compensation technique; threshold voltage; ultrathin buried nitride integration; voltage -0.2 V; voltage 4 mV; Bismuth; CMOS integrated circuits; Hot carrier injection; Logic gates; MOS devices; Performance evaluation; Substrates;
Conference_Titel :
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-9949-6
