Title :
A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture
Author :
Yamase, Tomoyuki ; Uchida, Hiroaki ; Noguchi, Hidemi
Author_Institution :
Syst. IP Core Labs., NEC Corp., Kawasaki, Japan
Abstract :
We have developed a 7-b 1.3-GSa/s 1-bit/stage pipeline ADC with a folding characteristic that uses a polarity selecting technique. The ADC achieves an ENOB of 6.5-b and consumes only 22 mW from 1.2V supply. These results yield a figure of merit (FOM) of 190-fJ/conv.-step. It is implemented in 45-nm CMOS technology and occupies a core area of 0.023 mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; CMOS technology; ENOB; FOM; figure of merit; folding characteristic; folding converter architecture; pipeline ADC; polarity selecting technique; power 22 mW; size 45 nm; voltage 1.2 V; CMOS integrated circuits; Digital signal processing; Frequency measurement; Interpolation; Logic gates; Pipelines; Signal resolution;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
