DocumentCode
549813
Title
A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC
Author
Miyahara, Masaya ; Lee, Hyunui ; Paik, Daehwa ; Matsuzawa, Akira
Author_Institution
Tokyo Inst. of Technol., Tokyo, Japan
fYear
2011
fDate
15-17 June 2011
Firstpage
126
Lastpage
127
Abstract
An open-loop interpolated pipeline ADC is proposed. Weight controlled capacitor arrays are introduced to realize an interpolation and a pipelined operation with open-loop amplifiers. The 10-bit ADC fabricated in 90 nm CMOS demonstrates ENOB of 8.5b over 80 MHz bandwidth (BW) and a conversion rate of 320 MS/s without linearity compensation and consumes 40 mW. The FoMs are 780 fJ/c.-s. defined by the 80 MHz BW and 390 fJ/c.-s. defined by the 320 MSps conversion rate with a BW of 80 MHz.
Keywords
CMOS analogue integrated circuits; amplifiers; analogue-digital conversion; interpolation; CMOS; ENOB; bandwidth 80 MHz; open-loop amplifier; open-loop interpolated pipeline ADC; power 40 mW; size 90 nm; weight controlled capacitor array; word length 10 bit; Arrays; CMOS integrated circuits; Capacitance; Capacitors; Interpolation; Linearity; Pipelines; ADC; interpolation and CMOS; open loop; pipeline;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986069
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