• DocumentCode
    549814
  • Title

    A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS

  • Author

    Chung, Yung-Hui ; Wu, Jieh-Tsorng

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    2011
  • fDate
    15-17 June 2011
  • Firstpage
    128
  • Lastpage
    129
  • Abstract
    An 8-bit subranging ADC was fabricated using a 55nm CMOS technology. To enhance speed, subranging is executed by activating comparators in the digital domain. To save power, comparators are latches with automatic offset calibration. Operating at 1GHz sampling rate, the ADC consumes 16mW from a 1.2V supply. The measured DNL is 0.8LSB and INL is 1.2LSB. The measured SFDR and SNDR are 55dB and 43.5dB respectively. The ADC occupies an active area of 0.2mm2. Its FOM is 125fJ/conversion-step.
  • Keywords
    CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); 8-bit subranging ADC; CMOS technology; FOM; SFDR; SNDR; automatic offset calibration; comparator; frequency 1 GHz; power 16 mW; size 55 nm; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Calibration; Capacitors; Latches; Semiconductor device measurement; Very large scale integration; Analog-digital conversion; calibration; comparators (circuits); subranging ADC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Type

    conf

  • Filename
    5986070
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549814