Title :
A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder
Author :
Chen, Chih-Lung ; Lin, Yu-Hsiang ; Chang, Hsie-Chia ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, a (491, 3, 6) time-varying LDPC-CC decoder chip supporting five code-rates is implemented in 90nm CMOS technology. The decoder containing 5 processors occupies 2.24 mm2 and provides twice faster decoding convergence speed. Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with a 0.024 nJ/bit/proc energy efficiency.
Keywords :
CMOS integrated circuits; codecs; parity check codes; (491,3,6) time-varying LDPC-CC decoder chip; CMOS technology; bit rate 2.37 Gbit/s; decoding convergence speed; five code-rates; low-density parity-check convolutional codes; power 284.8 mW; size 90 nm; voltage 1.2 V; Decoding; Energy measurement; Frequency measurement; Program processors; Size measurement; Throughput; Voltage measurement; LDPC-CC; high throughput;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
