Title :
Adaptive robustness tuning for high performance domino logic
Author :
Giridhar, Bharan ; Fick, David ; Fojtik, Matthew ; Satpathy, Sudhir ; Bull, David ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
A new domino design style is proposed that provides performance gains of up to 71% over conventional domino, and is demonstrated in a 32b multiplier in 65nm CMOS. The design dynamically tunes domino gates to trade surplus noise margins at nominal conditions for performance by detecting stability errors during runtime while guaranteeing correct operation.
Keywords :
CMOS logic circuits; circuit noise; circuit stability; circuit tuning; logic gates; multiplying circuits; CMOS; adaptive robustness tuning; domino design style; domino gate; high performance domino logic; multiplier; size 65 nm; stability error; surplus noise margin; CMOS integrated circuits; Latches; Logic gates; Robustness; Subspace constraints; Tuning; Voltage measurement;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
