Title :
A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping
Author :
Dighe, Saurabh ; Gupta, Sumeet ; De, Vivek ; Vangal, Sriram ; Borkar, Nitin ; Borkar, Shekhar ; Roy, Kaushik
Abstract :
This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.
Keywords :
microprocessor chips; power aware computing; voltage regulators; IA processor; core computation energy; energy efficiency; on-package voltage regulator; optimal core mapping scheme; size 45 nm; variation-aware dynamic voltage frequency scaling; variation-aware scheduling; voltage rails; within-die core-to-core maximum operational frequency; Energy efficiency; Energy measurement; Frequency measurement; Semiconductor device measurement; Temperature measurement; Thermal sensors; Voltage measurement;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
