A digital CDS scheme on fully column-inline TDC architecture for an APS-C format CMOS image sensor

Author

Takahashi, Tomohiro ; Ui, Hiroki ; Takatori, Nozomu ; Sanada, Shingo ; Hamamoto, Takeshige ; Nakayama, Hideo ; Moriyama, Yusuke ; Akahide, Miho ; Ueno, Takahisa ; Fukushima, Noriyuki

Author_Institution

Sony Corp., Atsugi, Japan

fYear

2011

fDate

15-17 June 2011

Firstpage

90

Lastpage

91

Abstract

This paper proposes a digital correlate double sampling (CDS) scheme which is suitable for a column-inline time to digital converter (TDC). The column-parallel TDCs, where measurements are made with a counter and delay line interpolation, achieve high speed A/D conversion without decreasing resolution. An APS-C format image sensor with 12-bit 360 Mpixel/s readout is realized in a cost-effective 0.18-μm CMOS technology.

Keywords

CMOS image sensors; image convertors; sampling methods; A/D conversion; APS-C format CMOS image sensor; CMOS technology; column-inline TDC architecture; column-parallel TDC; correlate double sampling; delay line interpolation; digital CDS scheme; size 0.18 mum; time to digital converter; word length 12 bit; CMOS image sensors; CMOS integrated circuits; Clocks; Decoding; Noise; Radiation detectors; Timing; CMOS image sensor; TDC; column-parallel architecture; correlate double sampling (CDS);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986399