Title :
A 12-ENOB 6X-OSR noise-shaped pipelined ADC utilizing a 9-bit linear front-end
Author :
Rajaee, O. ; Moon, U.
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
Abstract :
A noise-shaped pipelined ADC is presented in this paper. A minimal complexity Delta-Sigma modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18 μm CMOS, the ADC achieves 12 ENOB with 64 MHz clock at 6 X OSR.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; delta-sigma modulation; CMOS; delta-sigma modulator; high-order noise shaping; linear front-end; noise-shaped pipelined ADC; residue feedback; size 0.18 mum; word length 9 bit; Accuracy; Capacitors; Hafnium; Modulation; Noise; Noise shaping; Quantization;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
