DocumentCode
549873
Title
A 32nm, 1.05V, BIST enabled, 10–40MHz, 11-9 bit, 0.13mm2 digitized integrator MASH ΔΣ ADC
Author
Carlton, B.R. ; Lakdawala, H. ; Alpman, E. ; Rizk, J. ; Li, Y. William ; Perez-Esparza, B. ; Rivera, V. ; Nieva, C.F. ; Gordon, E. ; Hackney, P. ; Jan, C.-H. ; Young, I.A. ; Soumyanath, K.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2011
fDate
15-17 June 2011
Firstpage
36
Lastpage
37
Abstract
A 11-9 bit, 10-40MHz ΔΣ ADC using a digitized integrator (DI) MASH structure to allow for scalable, portable, and reconfigurable SoC solution in 32nm CMOS process is presented. An on-chip SNR calculator for high volume testing on a digital tester; startup automatic offset and reference calibration to prevent integrator overload due to manufacturing variations, and compensation for finite opamp gain. The ADC consumes 28mW at 1.05, occupies 0.13mm2.
Keywords
CMOS integrated circuits; analogue-digital conversion; built-in self test; system-on-chip; ΔΣ ADC; BIST; CMOS process; digital tester; digitized integrator MASH structure; finite opamp gain; frequency 10 MHz to 40 MHz; high volume testing; on-chip SNR calculator; power 28 mW; reconfigurable SoC solution; reference calibration; size 32 nm; startup automatic offset; voltage 1.05 V; word length 11 bit to 9 bit; Built-in self-test; Computer architecture; Latches; Multi-stage noise shaping; Sea measurements; Signal to noise ratio; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986412
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