A continuous-time, jitter insensitive ΣΔ modulator using a digitally linearized Gm-C integrator with embedded SC feedback DAC

This paper explores the use of a digitally linearized, low-power G_m-C integrator in the first stage of a 5^th order continuous time sigma-delta modulator. The proposed architecture features a jitter insensitive SC feedback and a noisy-but-linear auxiliary modulator that is employed to estimate the nonlinearities of the first integrator in the main signal path. A 65-nm CMOS experimental prototype achieves 79 dB dynamic range, 74.3 dB peak SNR and 73.3 dB peak SNDR for a signal bandwidth of 1.95 MHz and 124.8 MHz sampling rate. The IC dissipates 8.55 mW from a 2.5 V supply.