A 48-dB DR 80-MHz BW 8.88-GS/s bandpass ΔΣ ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

Author

Martens, Ewout ; Bourdoux, André ; Couvreur, Aissa ; Van Wesemael, Peter ; Van der Plas, Geert ; Craninckx, Jan ; Ryckaert, Julien

Author_Institution

IMEC, Leuven, Belgium

fYear

2011

fDate

15-17 June 2011

Firstpage

40

Lastpage

41

Abstract

A 2.22GHz 4^th-order BP ΔΣ ADC has been realized in 40nm CMOS. The test chip contains a complete system consisting of the ADC core, the PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers are 6 times interleaved enabling a polyphase structure for the DFD and relaxing speed requirements. Sampled at 8.88GS/s the ADC achieves a DR of 48dB in a band of 80MHz with an IIP3 of +1dBm.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; band-pass filters; delta-sigma modulation; digital filters; phase locked loops; 4^th-order bandpass ΔΣ ADC; CMOS; RF digitization; clock generation network; digital decimation filters; down conversion; frequency 80 MHz; gain 48 dB; integrated PLL; polyphase structure; relaxing speed requirements; size 40 nm; Band pass filters; CMOS integrated circuits; Clocks; Computer architecture; Phase locked loops; Radio frequency; Resonator filters; ΔΣ ADC; RF bandpass filters; decimation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986414