A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz fT BiCMOS process

Author

Poulton, Ken ; Jewett, Bob ; Liu, Jacky

Author_Institution

Agilent Technol., Santa Clara, CA, USA

fYear

2011

fDate

15-17 June 2011

Firstpage

62

Lastpage

63

Abstract

We describe a DAC which can operate at up to 7.2 GSa/s with 14-bit resolution or up to 12 GSa/s with 12-bit resolution. It uses a segmented architecture, with an R/2R ladder for the 10 LSBs; distributed resampling is applied to all current sources. The DAC achieves an SFDR of 77 dB at low output frequencies and an SFDR of 67 dB and an SNR of 62 dB from DC to 3 GHz. It demonstrates a phase noise of -157 dBc/Hz at 10 kHz from a 1 GHz carrier, 22 dB better than synthesized signal generation instruments. The DAC is built in a 165-GHz f_T, 130-nm BiCMOS process and packaged in a 780-ball BGA.

Keywords

BiCMOS digital integrated circuits; digital-analogue conversion; phase noise; BGA packaging; BiCMOS process; DAC; R/2R ladder; SFDR; distributed resampling; frequency 165 GHz; phase noise; size 130 nm; word length 12 bit; word length 14 bit; BiCMOS integrated circuits; CMOS integrated circuits; Clocks; Distributed databases; Instruments; Phase noise; Switches; 14-bit; BiCMOS; DAC; R/2R; SFDR; phase noise; resampling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986425