Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control

Author

Matsunaga, Shoun ; Katsumata, Akira ; Natsui, Masanori ; Fukami, Shunsuke ; Endoh, Tetsuo ; Ohno, Hideo ; Hanyu, Takahiro

Author_Institution

Center for Spintronics Integrated Syst., Tohoku Univ., Sendai, Japan

fYear

2011

fDate

15-17 June 2011

Firstpage

298

Lastpage

299

Abstract

A six-MOS-transistor/two-MTJ-device (6T-2MTJ)-based cell circuit with an autonomous leakage-current control mechanism is proposed and fabricated for a fully parallel nonvolatile TCAM. A diode-connected nMOS transistor is inserted into each cell for match-line discharge control, which enables bit-parallel equality-search operation more than 144 bits. Since each match line is divided into three segments, the activity rate of cells is reduced to 2.8%. This almost eliminates leakage power while maintaining comparable search energy of 1.04 fJ/bit/search in comparison with a CMOS-based TCAM.

Keywords

CMOS memory circuits; MRAM devices; content-addressable storage; leakage currents; magnetic tunnelling; autonomous leakage-current control mechanism; bit-parallel equality-search operation; diode-connected nMOS transistor; fully parallel 6T-2MTJ nonvolatile TCAM; magnetic tunnel junction devices; single-transistor-based self match-line discharge control; ternary content-addressable memories; Arrays; Discharges; Magnetic tunneling; Nonvolatile memory; Semiconductor device measurement; Voltage control; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986429