Title :
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell
Author :
Cheng, K. ; Khakifirooz, A. ; Kulkarni, P. ; Ponoth, S. ; Haran, B. ; Kumar, A. ; Adam, T. ; Reznicek, A. ; Loubet, N. ; He, H. ; Kuss, J. ; Wang, M. ; Levin, T.M. ; Monsieur, F. ; Liu, Q. ; Sreenivasan, R. ; Cai, J. ; Kimball, A. ; Mehta, S. ; Luning, S.
Author_Institution :
Albany Nanotech, IBM, Albany, NY, USA
Abstract :
For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 μA/μm at Ioff = 100 nA/μm for high performance (HP) and 920/880 μA/μm at Ioff = 1 nA/μm for low power (LP), respectively, at VDD = 1 V. High density 6-T SRAM cells down to 0.08 μm2 are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive LG scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; system-on-chip; SRAM cell; capacitance reduction; extremely thin SOI CMOS; gate length; gate pitch; low power electronics; multiVt transistors; size 22 nm; system-on-chip applications; CMOS integrated circuits; Capacitance; Epitaxial growth; Logic gates; Random access memory; System-on-a-chip; Transistors;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
