Title :
A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation
Author :
Rao, Sachin ; Young, Brian ; Elshazly, Amr ; Yin, Wenjing ; Sasidhar, Naga ; Hanumolu, Pavan Kumar
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
Abstract :
A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90 nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8 MHz signal bandwidth and consumes 4.3 mW.
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; pulse width modulation; voltage-controlled oscillators; 2-level PWM modulation; CMOS process; SFDR open loop VCO-based ADC; bandwidth 8 MHz; distortion elimination; highly linear calibration free VCO-based ADC; multilevel feedback DAC; power 4.3 mW; size 90 nm; Calibration; Modulation; Power harmonic filters; Time domain analysis; Time varying systems; Tuning; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
