DocumentCode
549907
Title
10Gb/s serial I/O receiver based on variable reference ADC
Author
Chen, E-Hung ; Yousry, Ramy ; Ali, Tamer ; Yang, Chih-Kong Ken
Author_Institution
Univ. of California, Los Angeles, CA, USA
fYear
2011
fDate
15-17 June 2011
Firstpage
288
Lastpage
289
Abstract
ADC-based serial I/O receiver draws growing interest with technology scaling. Power consumption remains among the key issues for both the high-speed ADC and the high-throughput DSP. This paper presents an ADC-based receiver that relaxes the ADC requirements with a simple mixed-mode pre-equalizer. Variable ADC reference level compensates for both the frontend non-ideality and the channel response while maintaining low ADC resolution.
Keywords
analogue-digital conversion; digital signal processing chips; mixed analogue-digital integrated circuits; power consumption; ADC-based receiver; bit rate 10 Gbit/s; channel response; high-throughput DSP; mixed-mode pre-equalizer; power consumption; serial I/O receiver; technology scaling; variable ADC reference level; variable reference ADC; CMOS technology; Decision feedback equalizers; Finite impulse response filter; Optimized production technology; Receivers; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986457
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