Author :
Janssen, E. ; Doris, K. ; Zanikopoulos, A. ; van der Weide, G. ; Vertregt, M. ; Jamin, O. ; Courtois, F. ; Blard, N. ; Kristen, M. ; Bertrand, S. ; Riviere, F. ; Deforeit, F. ; Blanc, G. ; Penning, Y. ; Lefebvre, F. ; Viguier, D. ; Dubois, M. ; Vrignaud,
Abstract :
This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; cable television; phase locked loops; CMOS; DOCSIS 3.0; PLL; digital multichannel selection filter; direct sampling multichannel receiver; power 980 mW; size 65 nm; time-interleaved ADC; Baseband; Cable TV; Frequency domain analysis; Radio frequency; Receivers; Signal to noise ratio; Tuners;
