Oscillator noise budget for ADC systems

This paper presents a model that can be used to estimate, or design, a system consisting of a crystal oscillator (clock generator) and an analog-to-digital converter (ADC). The model is built based on a comprehensive analysis of the clock generation as a noise source, and its influence on the ADC signal-to-noise ratio specification. The model has as inputs the main noise sources, including a clock with jitter (or phase noise) specifications, and an ADC, being the output an FFT spectrum for verification of the system design specifications. The complete design flow is presented for the case where the ADC specifications are known and the crystal oscillator specifications are determined from the system specifications. The model is validated through the simulation of both, the crystal oscillator and the ADC, at transistor level. It confirms that the jitter analysis, the model predictions and the oscillator design flow are valid, showing it is a useful tool to assist at system design.