Logic simulation acceleration based on GPU

Simulation overhead becomes more decisive for VLSI design cost. A parallel method to accelerate VLSI logic simulation with GPGPU is addressed in this paper. To explore further parallelism and locality of logic simulation, we present an adaptable partition strategy to achieve variable coarse-grain partitioning targets on the GPU platform, which varies with the load balance factor in parallel threads and the architecture feature of GPU platform. Our experiments demonstrate that using the NVIDIA CUDA technology results in a significant speedup of logic simulation, maximal speedups of up to factor 21 comparing with single core computation.