PMOS drain-bulk connected loads for Subthreshold Source-Coupled Logic

This paper aims to prove the usefulness of PMOS drain-bulk connected transistors for use as loads in implementing Subthreshold Source-Coupled Logic (STSCL) circuits. Measurements performed on a 180nm wafer as well as simulations with the EKV 301.02 model following a parameter extraction on the used technology, confirm that the desirable output voltage swing needed for robust operation in the subthreshold (weak inversion) region, can only be achieved through the use of PMOS drain-bulk connected transistors as loading elements.