Closed-form expressions for the coupling capacitance computation between through silicon vias and interconnects for 3D ICs

Author

Bontzios, Yiorgos I. ; Dimopoulos, Michael G. ; Hatzopoulos, Alkis A.

Author_Institution

Dept. of Electr. & Comput. Eng., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

fYear

2011

fDate

16-18 June 2011

Firstpage

77

Lastpage

81

Abstract

Three dimensional (3D) integration attempts to keep Moore´s Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the capacitive coupling between TSVs and (horizontal) interconnects is studied. A closed-form formula is derived by studying the physics of the problem. In the analysis, no fitting techniques are utilized. As results show, the range of validity of the proposed formula covers the current and future TSV geometries with the average error falling within 4-6%.

Keywords

coupled circuits; integrated circuit interconnections; three-dimensional integrated circuits; 3D IC; Moore´s law; closed-form expressions; coupling capacitance computation; horizontal interconnects; three dimensional integration; through silicon vias; Capacitance; Couplings; Geometry; Integrated circuit interconnections; Metals; Silicon; Through-silicon vias; CMOS; Capacitive coupling; Interconnects; Mixed-signal RF; Through silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference

Conference_Location

Gliwice

Print_ISBN

978-1-4577-0304-1

Type

conf

Filename

6016039