• DocumentCode
    55345
  • Title

    Concurrent Path Selection Algorithm in Statistical Timing Analysis

  • Author

    Jaeyong Chung ; Abraham, J.A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
  • Volume
    21
  • Issue
    9
  • fYear
    2013
  • fDate
    Sept. 2013
  • Firstpage
    1715
  • Lastpage
    1726
  • Abstract
    Circuit timing is becoming more and more uncertain under greater process variation as technology scales. Given the fault probability of each timing path and their statistical correlation from a statistical timing framework, the path selection problem for delay faults has a nature similar to the problem of designing a portfolio of stocks or assets or determining the size of bets in gambling to minimize risk. This observation allows us to develop a very different path selection approach from the conventional ones. If selection of k paths is required in a set of paths, we partition the set into two path sets and determine how many paths should be selected in each path set out of the k paths based on the probabilities of each path set containing faulty paths. We recursively continue this process, which results in the paths to be targeted during tests. The partitioning is easily performed because the paths are already grouped into the depth-first search tree based on their suffix or prefix. Experimental results show that the proposed algorithm can effectively use the correlation to generate high-quality path sets. In addition, we study the issues that occur after automatic test pattern generation on the selected paths, and discuss possible solutions to them.
  • Keywords
    automatic test pattern generation; circuit testing; failure analysis; tree searching; automatic test pattern generation; circuit timing; concurrent path selection algorithm; delay faults; depth-first search tree; fault probability; faulty path; high-quality path set; path set probability; process variation; statistical correlation; statistical timing analysis; statistical timing framework; timing path; Circuit faults; Correlation; Decision trees; Delay; Games; Probability; Path selection; process variation; statistical timing analysis;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2218136
  • Filename
    6329455