Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21μA in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as 8kV HBM and 800V MM) in a 65-nm CMOS technology.