FPGA design of a variable sampling period PLL with a Digital Notch Filter for distorted grids

This paper describes the implementation of a novel three-phase PLL for distorted grids in a Field Programmable Gate Array (FPGA). It is based on the concept of a variable sampling period, which allows to automatically adjust the sampling frequency to be an integer multiple of the line frequency and a Digital Notch Filter (DNF), which is used in the loop to reject disturbances, such as unbalanced voltage and harmonics. Structural simplicity, robustness and harmonics rejection are some of the attractive features offered by the proposed system.