DocumentCode
555110
Title
Probabilistic Instruction Cache Analysis Using Bayesian Networks
Author
Bartlett, Marnie ; Bate, Iain ; Cussens, J. ; Kazakov, Dimitar
Author_Institution
Dept. of Comput. Sci., Univ. of York, York, UK
Volume
1
fYear
2011
fDate
28-31 Aug. 2011
Firstpage
233
Lastpage
242
Abstract
Current approaches to instruction cache analysis for determining worst-case execution time rely on building a mathematical model of the cache that tracks its contents at all points in the program. This requires perfect knowledge of the functional behaviour of the cache and may result in extreme complexity and pessimism if many alternative paths through code sections are possible. To overcome these issues, this paper proposes a new hybrid approach in which information obtained from program traces is used to automate the construction of a model of how the cache is used. The resulting model involves the learning of a Bayesian network that predicts which instructions result in cache misses as a function of previously taken paths. The model can then be utilised to predict cache misses for previously unseen inputs and paths. The accuracy of this learned model is assessed against real benchmarks and an established statistical approach to illustrate its benefits.
Keywords
belief networks; cache storage; program diagnostics; statistical analysis; Bayesian networks; probabilistic instruction cache analysis; program traces; statistical approach; worst-case execution time; Analytical models; Bayesian methods; Data models; Hardware; Predictive models; Program processors; Real time systems; Bayesian network; instruction cache; worst-case execution time (WCET);
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded and Real-Time Computing Systems and Applications (RTCSA), 2011 IEEE 17th International Conference on
Conference_Location
Toyama
ISSN
1533-2306
Print_ISBN
978-1-4577-1118-3
Type
conf
DOI
10.1109/RTCSA.2011.55
Filename
6029853
Link To Document