DocumentCode :
555287
Title :
Coverage guided systematic concurrency testing
Author :
Wang, Chao ; Said, Mahmoud ; Gupta, Aarti
Author_Institution :
NEC Labs. America, USA
fYear :
2011
fDate :
21-28 May 2011
Firstpage :
221
Lastpage :
230
Abstract :
Shared-memory multi-threaded programs are notoriously difficult to test, and because of the often astronomically large number of thread schedules, testing all possible interleavings is practically infeasible. In this paper we propose a coverage-guided systematic testing framework, where we use dynamically learned ordering constraints over shared object accesses to select only high-risk interleavings for test execution. An interleaving is of high-risk if it has not been covered by the ordering constraints, meaning that it has concurrency scenarios that have not been tested. Our method consists of two components. First, we utilize dynamic information collected from good test runs to learn ordering constraints over the memory-accessing and synchronization statements. These ordering constraints are treated as likely invariants since they are respected by all the tested runs. Second, during the process of systematic testing, we use the learned ordering constraints to guide the selection of interleavings for future test execution. Our experiments on public domain multithreaded C/C++ programs show that, by focusing on only the high-risk interleavings rather than enumerating all possible interleavings, our method can increase the coverage of important concurrency scenarios with a reasonable cost and detect most of the concurrency bugs in practice.
Keywords :
C++ language; concurrency theory; constraint handling; interleaved storage; multi-threading; program testing; public domain software; shared memory systems; C; C++; concurrency testing; coverage-guided systematic testing; dynamic information collection; interleavings; learned ordering constraints; memory access; multi-threaded programs; public domain programs; shared memory program; shared object accesses; synchronization statements; test execution; Computer bugs; Concurrent computing; Instruction sets; Reactive power; Schedules; Systematics; Testing; concurrency; coverage; partial order reduction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Software Engineering (ICSE), 2011 33rd International Conference on
Conference_Location :
Honolulu, HI
ISSN :
0270-5257
Print_ISBN :
978-1-4503-0445-0
Electronic_ISBN :
0270-5257
Type :
conf
DOI :
10.1145/1985793.1985824
Filename :
6032461
Link To Document :
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