3D electro-thermal simulations of analog ICs carried out with standard CAD tools and Verilog-A

High power density in integrated systems creates rises of temperature and gradient across the chip that can deteriorate the electrical performances of the system. In 3D stacked technologies, on chip power density will be even more important while heat spreading will be reduced leading to more thermal issues. Thus, it is very important for designers to have a powerful and reliable electro-thermal simulator. This paper presents a designer friendly efficient direct electro-thermal simulator integrated in the Cadence^® environment that couples the electrical schematic to its thermal network. The comparison between experimental and simulation results of a test chip are given to validate the simulator.