The design of a run-time monitoring structure for a MPSoC

MPSoC (MultiProcessor System on Chip) are computing architectures that employ multiple processing cores on the same chip in order to provide the required level of performance and power dissipation for the running applications. MPSoC are attractive because they allow the execution of complex embedded applications that are made of multiple tasks. The tasks are concurrently executed on the available processing cores of the MPSoC and exchange data using the memory resources that may be organized as FIFO buffers. The applications may have real time constraints and in this case any missing deadline may negatively alter the quality of service provided by the system. This paper presents a method that can be used to detect timeliness violations inside a MPSoC. The processing cores of the MPSoC are augmented with a monitoring structure that watches over the communication infrastructure inside the MPSoC. All data transfers are recorded and their timing is compared against a reference expected behavior. If abnormal execution is detected then an exception may be triggered and serviced in a manner suitable for the applications.