Investigation of Electrostatic Integrity of Nanoscale Dual Material Gate Dielectric Pocket Silicon-on-Void (DMGDPSOV) MOSFET for Improved Device Scalability

This paper presents a 2-D temperature-dependent analytical drain current model, which is valid for six different device architectures (by slightly modifying the used parameters), i.e., dual material gate dielectric pocket silicon-on-void, dual material gate silicon-on-void, dual material gate silicon-on-insulator, dielectric pocket silicon-on-void, silicon-on-void, and silicon-on-insulator MOSFETs. The results thus obtained, i.e., drain current, transconductance, g_m/I_ds ratio, threshold voltage, subthreshold slope, and I_on/I_off ratio have been verified with the simulated results obtained using ATLAS 3-D device simulator for channel length down to 30 nm. The analytical model is also used to investigate the impact of temperature variation on the characteristics of N-MOS inverter based on different architectures. In addition, impact of process and parameters variation (i.e., variation in shallow extension depth (X_e), side pillar thickness (T_st), thickness of buried oxide layer (t₃) along with the variation in temperature) on the subthreshold performance of different devices has also been studied through exhaustive device simulation.