DocumentCode
557326
Title
CMOS-compatible aligned fusion wafer bonding
Author
Dragoi, V. ; Mittendorfer, G. ; Flötgen, C. ; Dussault, D. ; Wagenleitner, T.
Author_Institution
EV Group, St. Florian, Austria
Volume
1
fYear
2011
fDate
17-19 Oct. 2011
Firstpage
141
Lastpage
144
Abstract
Wafer bonding is a very attractive technology for applications in wafer-level 3D integration. However, most of the bonding processes are not compatible with CMOS technology in terms of process temperature and contamination levels. A low temperature fusion bonding process is presented as an example of how the wafer bonding issues were successfully solved and applied to manufacturing processes.
Keywords
CMOS image sensors; plasma materials processing; wafer bonding; CMOS technology; CMOS-compatible aligned fusion wafer bonding; bonding processes; contamination levels; low temperature fusion bonding process; manufacturing processes; process temperature; wafer-level 3D integration; Bonding; CMOS integrated circuits; Cleaning; Optical imaging; Plasmas; Silicon; Wafer bonding; 3D integration; CMOS image sensor; back-side illumination; optical alignment; plasma activated wafer bonding; single wafer cleaning;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference (CAS), 2011 International
Conference_Location
Sinaia
ISSN
1545-827X
Print_ISBN
978-1-61284-173-1
Type
conf
DOI
10.1109/SMICND.2011.6095739
Filename
6095739
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