Effects of inter-Chip and intra-Chip electromagnetic interferences on PLL frequency pulling and spurs

System-level inter-Chip and intra-Chip interferences analysis and characterization is proposed. Inter-Chip noise interferences as function of wireless coupling-path attributes (wireless separation distance between emitter and receiver chips, injected power levels, Charge-Pump-Current) are characterized. At Intra-Chip level, influence of VCO-PLL inductance architecture (8-shaped topology versus O-shaped topology) on noise interferences is evaluated through comparisons between library-models, full-wave EM analysis and measurement characterization. Intentional interruptions based FIBs (Focused Ion Beam) cutting of identified critical power/ground paths show the importance of electromagnetic coupling. Impact of intra-Chip and inter-Chip couplings on frequency pulling of integrated PLL circuits is experimentally evaluated.