• DocumentCode
    560129
  • Title

    Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s

  • Author

    Luisier, Mathieu ; Boykin, Timothy B. ; Klimeck, Gerhard ; Fichtner, Wolfgang

  • Author_Institution
    Network for Comput. Nanotechnol., Purdue Univ., West Lafayette, IN, USA
  • fYear
    2011
  • fDate
    12-18 Nov. 2011
  • Firstpage
    1
  • Lastpage
    11
  • Abstract
    We present a multi-dimensional, atomistic, quantum transport simulation approach to investigate the performances of realistic nanoscale transistors for various geometries and material systems. The central computation consists in solving the Schrodinger equation with open boundary conditions several thousand times. To do that, a Wave Function approach is used since it can be relatively easily parallelized. To further improve the computational efficiency, three additional levels of parallelization are identified, the work load is optimally balanced between the CPUs, computational interleaving is applied where possible, and a mixed precision scheme is introduced. Using two different device types, a high electron mobility and a band-to-band tunneling transistor, sustained performances up to 1.28 PFlop/s in double precision (55% of the peak performance) and 1.44 PFlop/s in mixed precision are reached on 221,400 cores on the CRAY-XT5 Jaguar at Oak Ridge National Lab.
  • Keywords
    Schrodinger equation; high electron mobility transistors; multiprocessing systems; nanoelectronics; performance evaluation; tunnelling; wave functions; CRAY-XT5 Jaguar; Oak Ridge National Lab; Schrodinger equation; atomistic nanoelectronic device engineering; band-to-band tunneling transistor; computational interleaving; high electron mobility transistor; mixed precision scheme; multidimensional quantum transport simulation approach; open boundary conditions; realistic nanoscale transistors; wave function approach; Atomic layer deposition; Equations; Mathematical model; Nanoscale devices; Performance evaluation; Sparse matrices; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for
  • Conference_Location
    Seatle, WA
  • Electronic_ISBN
    978-1-4503-0771-0
  • Type

    conf

  • Filename
    6114391