Implementation of a reprogrammable DSP/FPGA based platform for real-time HD video coding

Author

Fiorucc, Federico ; Verducci, Ludovico ; Micanti, Paolo ; Baruffa, G. ; Frescura, Fabrizio

Author_Institution

Dept. of Electron. & Inf. Eng., Univ. of Perugia, Perugia, Italy

fYear

2010

fDate

1-2 Dec. 2010

Firstpage

185

Lastpage

189

Abstract

In this paper we present the architecture of a DSP/FPGA based hardware platform, conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD resolutions, have been simulated and their performance found on the embedded processing cores. The TI TMS320C6455 DSP has been selected for the instruction set dedicated to Galois field arithmetic, used in the JPWL standard. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability.

Keywords

Galois fields; digital signal processing chips; field programmable gate arrays; instruction sets; parallel architectures; reconfigurable architectures; signal resolution; video coding; Galois field arithmetic; H.264; JPEG 2000; JPWL standard; TI TMS320C6455 DSP; architecture modularity; board parallelization; embedded processing core; encoding; high definition video processing; instruction set; performance scalability; programmable logic processing; real-time HD video coding; reconfigurable system; reprogrammable DSP-FPGA based platform; scalable system; super HD resolution; Digital signal processing; Field programmable gate arrays; IEC; IEC standards; Image coding; Streaming media; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Education and Research Conference (EDERC), 2010 4th European

Conference_Location

Nice

Print_ISBN

978-0-9552047-4-6

Type

conf

Filename

6151433