DSP implementation of on-board distributed video coding

Author

Zheng, Min ; Ali, Falah H.

Author_Institution

Sch. of Eng. & Design, Univ. of Sussex, Brighton, UK

fYear

2010

fDate

1-2 Dec. 2010

Firstpage

250

Lastpage

254

Abstract

The first implementation of a distributed video encoder, to the best knowledge of the authors, on a Texas Instruments TMS320DM6437 digital signal processor (DSP) is described in this paper. The encoder consists of a Wyner-Ziv (WZ) encoder and a conventional intra-frame encoder. The WZ encoder is efficiently implemented, using rate adaptive low-density-parity-check accumulative (LDPCA) codes, exploiting the hardware features and optimization techniques to improve the overall performance. Implementation results show that the WZ encoder is able to encode at 134M instruction cycles per QCIF frame on a TMS320DM6437 DSP running at 700MHz. This results in encoder speed 29 times faster than non-optimized encoder implementation.

Keywords

adaptive codes; digital signal processing chips; optimisation; parity check codes; video coding; LDPCA codes; TMS320DM6437 digital signal processor; Texas Instruments; Wyner-Ziv encoder; distributed video encoder; intra-frame encoder; low-density-parity-check accumulative codes; on-board distributed video coding; optimization; rate adaptive codes; Computer architecture; Decoding; ISO standards; Joints; Phase locked loops; Robustness; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Education and Research Conference (EDERC), 2010 4th European

Conference_Location

Nice

Print_ISBN

978-0-9552047-4-6

Type

conf

Filename

6151446