DSP implementation of on-board distributed video coding

The first implementation of a distributed video encoder, to the best knowledge of the authors, on a Texas Instruments TMS320DM6437 digital signal processor (DSP) is described in this paper. The encoder consists of a Wyner-Ziv (WZ) encoder and a conventional intra-frame encoder. The WZ encoder is efficiently implemented, using rate adaptive low-density-parity-check accumulative (LDPCA) codes, exploiting the hardware features and optimization techniques to improve the overall performance. Implementation results show that the WZ encoder is able to encode at 134M instruction cycles per QCIF frame on a TMS320DM6437 DSP running at 700MHz. This results in encoder speed 29 times faster than non-optimized encoder implementation.