A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications

Standard cache memories exploit 1-D spatial locality which will suffer great performance penalty when applied to multimedia that manifests 2-D data dependence. History-based prefetching policies have been proposed to tailor cache memories to multimedia applications. Such schemes, however, are driven by the instruction address, which means it needs a significantly large prediction table for instruction caching. In this paper we propose a novel data address directed scheme to pure hardware prefetching. The prefetching scheme is modeled and evaluated at transaction level (TLM) based on Carbon SoC Designer. The experimental results show that data address directed prefetching-on-miss policy can significantly reduce cache miss rate by up to 23.8% with only a small prediction table.