BIST using genetic algorithm for error detection and correction

This paper presents a low peak power consumption BIST based on genetic algorithm (GA) is applied for viterbi decoder error detection and correction, denoted by GAITPGEDC. This method aims at reducing the changes between successive test pattern. Here m-1 test vectors are inserted between two successive n-bit generated by linear feedback shift registers (LFSR), where m and elements of group were optimized by GA. Thus the switching activities of test vectors are greatly reduced in test mode without compromising fault coverage. The proposed structure has the advantages of low test. Experiments conducted on ISCAS´89 benchmark circuits demonstrate that proposed scheme gives better fault coverage and with viterbi decoder error detection and correction was performed with a large reduction in power dissipation during testing.