Low power dual edge triggered flip-flop

Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the whole synchronous circuit. The pulse generator can be shared among many flip-flops to reduce the power dissipation. Firstly, in the Dual edge static pulsed flip-flop suffers from high leakage current leads to more power consumption. Secondly, Dual edge trigger sense amplifier flip-flop having unnecessary transitions which causes power consumption. Thirdly, Dual edge trigger NAND keeper flip-flop keeper technique is used to pull up the voltage to VDD having full swing and this keeper transistor width is high and which consumes more power. The power consumption of the Dual edge nand keeper flip-flop is 347uW. Lastly, Dual edge trigger pulsed flip-flop is introduced by employing a technique called conditional switching for further power reduction. The circuits are designed in a 0.18-um standard CMOS process with a 1.8V power supply voltage.