Reduction of leakage-power in CNTFET SRAM cell using stacked sleep technique at 32nm technology

As technology scales down both VDD and Vt has to decrease to maintain historical delay reduction, while restraining active power dissipation. Scaling of Vt however leads to substantial increase in the sub-threshold leakage power and it became a considerable constituent of the total dissipated power. Nowadays leakage power is the dominant component of the total power so it´s become important issue in processor hardware and software design. Carbon nanotubes with their superior properties have proved to be a potential alternative device to CMOS. Leakage power of caches, implemented using SRAM cells is a major source of power consumption in high performance microprocessors. In this paper, a new circuit-level state-saving ultra low-leakage technique is proposed and applied to CNTFET based SRAM Cell. This proposed CNTFET SRAM cell reduces leakage power by 96% compared to conventional CNTFET SRAM cell with minimal possible area and delay trade-off.