DocumentCode
562827
Title
Notice of Violation of IEEE Publication Principles
Power reduction in scan based BIST using BS-LFSR and scan-chain ordering
Author
Vijay, Rakshita ; Chitra, S.
Author_Institution
Dept. Of Electron. & Commun. Eng. (Appl. Electron.), Vandayar Eng. Coll., Thanjavur, India
fYear
2012
fDate
30-31 March 2012
Firstpage
534
Lastpage
540
Abstract
Notice of Violation of IEEE Publication Principles
"Power Reduction in Scan Based BIST Using BS-LFSR and Scan-Chain Ordering" by R. Vijay and S.Chitra
in the Proceedings of the 2012 International Conference on Advances in Engineering, Science and Management (ICAESM)
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper is a duplication of the original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"Bit Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak and Average-Power Reduction in Scan-Based BIST"
by Abdallatif S. Abu-Issa and Steven F. Quigley
in the IEEE Transactions on Computer-Aided Design of Design of Integrated Circuits and Systems, Vol 28, No 5, May 2009.
The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design. It has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), BIST technique uses linear feedback shift register (LFSR) for generating test pattern. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared - o those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time.
"Power Reduction in Scan Based BIST Using BS-LFSR and Scan-Chain Ordering" by R. Vijay and S.Chitra
in the Proceedings of the 2012 International Conference on Advances in Engineering, Science and Management (ICAESM)
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper is a duplication of the original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"Bit Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak and Average-Power Reduction in Scan-Based BIST"
by Abdallatif S. Abu-Issa and Steven F. Quigley
in the IEEE Transactions on Computer-Aided Design of Design of Integrated Circuits and Systems, Vol 28, No 5, May 2009.
The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design. It has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), BIST technique uses linear feedback shift register (LFSR) for generating test pattern. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared - o those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time.
Keywords
VLSI; built-in self test; circuit feedback; integrated circuit design; integrated circuit testing; low-power electronics; multiplexing equipment; shift registers; BS-LFSR; CUT; VLSI design; average-power reduction; bit-swapping LFSR; circuit under test; fault coverage; linear feedback shift register; low-power test; multiplexer; normal mode operation; peak-power reduction; power consumption; scan based BIST; scan shift operation; scan-based built-in self-test; scan-chain ordering; switching activity; test application time; test mode operation; test pattern generation; very large scale integration; Inverters; Multiplexing; Switches; Vectors; Built-in self-test (BIST); linear feedback shift register (LFSR); low-power test; pseudorandom pattern generator; scan-chain ordering; weighted switching activity (WSA);
fLanguage
English
Publisher
ieee
Conference_Titel
Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on
Conference_Location
Nagapattinam, Tamil Nadu
Print_ISBN
978-1-4673-0213-5
Type
conf
Filename
6216060
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