A new space vector pulse width modulation for reduction of common mode voltage in three level neutral point diode clamped multilevel inverter

In this paper, the space vector modulation technique for an neutral point clamped (NPC) three-level Inverter is described and investigation of the common mode voltage rejection also done. Based on the two level inverter, the paper further deals with space vector PWM technique for an three level inverter with 19 of 27 available voltage vectors are used in order to reduce the amplitude of CM voltage to be one sixth of the dc-link voltage by adding zero-sequence component to the fundamental component, thus selecting of the required voltage vector. The Simulation with a 1HP induction motor drive system is setup in Mat lab and the same results validated effectively by hardware -DSP 320F2812 processor and its shows that the CM voltage is effectively mitigated and the maximumoutput voltage is not affected.