Foreword Special Issue on Variation Aware Technology and Circuit Co-Design

Once considered mature and commodity technology, CMOS Si technology keeps revamping itself as a collection of most innovative technologies known to humanity at this given time. Beyond conventional vanilla scale of SiON/Poly planar bulk Si technology, lab-level experiments constantly become manufacturing reality, such as high-k, metal gate, FDSOI, FinFET, and many exotic patterning technologies. This rapid pace of new technology introduction to CMOS technology, however, requires much more sophisticated optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout, and circuit design in a holistic manner enables significant performance improvement while reducing overall power consumption with the least amount of area penalty.